Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits.
On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding.
Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, interconnect structures are formed on metallization layers, followed by the formation of under-bump metallurgy (UBM), and the mounting of solder balls. FIG. 1 is a cross-sectional view of a conventional interconnect structure used in the WLCSP. Metal line 102 is formed in a top metallization layer. Passivation layer 104 is formed over the top metallization layer. Aluminum pad 106 is formed on passivation layer 104, and is connected to metal line 102 through aluminum via 108.
Passivation layer 110 is formed on passivation layer 104 and aluminum pad 106, and an opening is formed in passivation layer 110 to expose aluminum pad 106. Polymer layer 112 is then formed on passivation layer 110, and is patterned to expose aluminum pad 106. Post-passivation interconnect (PPI) line 114 is then formed, followed by the formation of polymer layer 116, and under-bump metallurgy (UBM) 118. Solder ball 120 may then be mounted on UBM 118.
The existence of aluminum pad 106 and the connecting aluminum lines causes an increase in RC delay, which is the result of increased resistance of aluminum lines and aluminum pads, and the result of increased parasitic capacitance. An improved back end of process is thus needed to solve this problem.